MC68HC05P18 Datasheet, PDF (91/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
16-Bit Timer
Output Compare
The contents of the output compare registers are compared with the
contents of the free-running counter once every four PH2 clock cycles.
If a match is found, the output compare flag bit (OCF) is set and the
output level bit (OLVL) is clocked to the output latch. The values in the
output compare registers and output level bit should be changed after
each successful comparison to control an output waveform or to
establish a new elapsed timeout. An interrupt can also accompany a
successful output compare if the output compare interrupt enable bit
(OCIE) is set.
After a CPU write cycle to the MSB of the output compare register pair
(OCRH), the output compare function is inhibited until the least
significant bit (LSB) (OCRL) is written. Both bytes must be written if the
MSB is written. A write made only to the LSB will not inhibit the compare
function. The free-running counter increments every four PH2 clock
cycles. The minimum time required to update the output compare
registers is a function of software rather than hardware.
The output compare output level bit (OLVL) will be clocked to its output
latch regardless of the state of the output compare flag bit (OCF). A valid
output compare must occur before the OLVL bit is clocked to its output
latch (TCMP).
Since neither the output compare flag (OCF) nor the output compare
registers are affected by reset, care must be exercised when initializing
the output compare function. The following procedure is recommended:
1. Block interrupts by setting the I bit in the condition code register
(CCR).
2. Write the MSB of the output compare register pair (OCRH) to
inhibit further compares until the LSB is written.
3. Read the timer status register (TSR) to arm the output compare
flag (OCF).
4. Write the LSB of the output compare register pair (OCRL) to
enable the output compare function and to clear its flag (and
interrupt).
5. Unblock interrupts by clearing the I bit in the CCR.
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
16-Bit Timer
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Advance Information
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