MC68HC05P18 Datasheet, PDF (93/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
16-Bit Timer
Input Capture
Register name and address: ICRH — $0014
Bit 7
6
5
Read: ICRH7 ICRH6 ICRH5
Write:
Reset:
4
ICRH4
3
ICRH3
Unaffected by reset
2
ICRH2
1
ICRH1
Bit 0
ICRH0
Register name and address: ICRL — $0015
Bit 7
6
5
4
3
2
1
Read: ICRL7 ICRL6 ICRL5 ICRL4 ICRL3 ICRL2 ICRL1
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 10-8. Input Capture Registers (ICRH/ICRL)
Bit 0
ICRL0
The contents of the free-running counter are transferred to the input
capture registers on each proper signal transition regardless of the state
of the input capture flag bit (ICF) in register TSR. The input capture
registers always contain the free-running counter value which
corresponds to the most recent input capture.
After a read of the MSB of the input capture register pair (ICRH), counter
transfers are inhibited until the LSB of the register pair (ICRL) is also
read. This characteristic forces the minimum pulse period attainable to
be determined by the time required to execute an input capture software
routine in an application.
Reading the LSB of the input capture register pair (ICRL) does not inhibit
transfer of the free-running counter. Again, minimum pulse periods are
ones which allow software to read the LSB of the register pair (ICRL) and
perform needed operations. There is no conflict between reading the
LSB (ICRL) and the free-running counter transfer, since they occur on
opposite edges of the PH2 clock.
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
16-Bit Timer
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Advance Information
93