MC68HC05P18 Datasheet, PDF (84/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Analog-to-Digital (A/D) Converter
9.6 A/D Conversion Data Register
This register contains the output of the A/D converter. See Figure 9-2.
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 9-2. A/D Conversion Data Register (ADC)
9.7 A/D Subsystem During Wait/Halt Modes
The A/D subsystem continues normal operation during wait mode and
halt mode. To decrease power consumption during wait or halt, the
ADON bit in the ADSC register and the EERC bit in the EEPROG
register should be cleared if the A/D subsystem is not being used.
9.8 A/D Subsystem Operation During Stop Mode
When stop mode is enabled, execution of the STOP instruction will
terminate all A/D subsystem functions. Any pending conversion is
aborted. When the oscillator resumes operation upon leaving stop
mode, a finite amount of time passes before the A/D subsystem
stabilizes sufficiently to provide conversions at its rated accuracy. The
delays built into the MC68HC805P18 when coming out of stop mode are
sufficient for this purpose. No explicit delays need to be added to the
application software.
Advance Information
84
MC68HC(8)05P18 — Rev. 2.0
Analog-to-Digital (A/D) Converter
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