MC68HC05P18 Datasheet, PDF (75/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
EEPROM
Mask Option Registers
8.5 Mask Option Registers
The mask option registers (MOR) consist of two EEPROM bytes located
at $3F00 and $3F01. The MORs hold the 16 option bits for:
• The SIOP data format, interrupt sensitivity
• COP enable/disable
• SIOP clock rate
• LVR enable/disable
• Stop conversion to halt, pullup/interrupt enable on port A
• Clock output option to replace PD5
When in the erased state, the EEPROM cells will read as logic 0s. These
registers are refreshed every 256 µs during power-on reset and every
16 ms after the part is out of reset (assuming f_OSC = 4 MHz).
Address: $3F00
Bit 7
6
5
4
3
2
1
Bit 0
Read: CLKOUT LVRE SWAIT SPR1 SPR0 LSBF LEVIRQ COPEN
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 8-2. Mask Option Register 1 (MOR1)
Address: $3F01
Bit 7
6
5
4
3
2
1
Read: PA7PU PA6PU PA5PU PA4PU PA3PU PA2PU PA1PU
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 8-3. Mask Option Register 2 (MOR2)
Bit 0
PA0PU
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
EEPROM
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Advance Information
75