MC68HC05P18 Datasheet, PDF (45/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Interrupts
Interrupt Types
4.3.3.1 External Interrupt (IRQ)
The IRQ pin drives an asynchronous interrupt to the CPU. An edge
detector flip-flop is latched on the falling edge of IRQ. If either the output
from the internal edge detector flip-flop or the level on the IRQ pin is low,
a request is synchronized to the CPU to generate the IRQ interrupt. If the
edge-sensitive only option is selected, the output of the internal edge
detector flip-flop is sampled and the input level on the IRQ pin is ignored.
If port A interrupts are programmed as an option, a port A interrupt will
use the same vector. The interrupt service routine address is specified
by the contents of memory locations $3FFA and $3FFB.
NOTE:
The internal interrupt latch is cleared nine PH2 clock cycles after the
interrupt is recognized (after location $3FFA is read). Therefore, another
external interrupt pulse could be latched during the IRQ service routine.
When the edge- and level-sensitive option is selected, the voltage
applied to the IRQ pin must return to the high state before the RTI
instruction in the interrupt service routine is executed.
The IRQ pin is one source of an IRQ interrupt and a mask option can
also enable the port A pins (PA0–PA7) to act as other IRQ interrupt
sources. These sources are all combined into a single ORing function to
be latched by the IRQ latch.
IRQ PIN
PA0
DDRA0
PA0 IRQ INHIBIT
(MASK OPTION)
:
:
:
:
PA7
DDRA7
PA7 IRQ INHIBIT
(MASK OPTION)
:
:
:
:
:
RST
IRQ VECTOR FETCH
MASK OPTION
(IRQ LEVEL)
V_DD
IRQ
LATCH
R
Figure 4-2. IRQ Function Block Diagram
TO BIH & BIL
INSTRUCTION
SENSING
TO IRQ
PROCESSING
IN CPU
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
Interrupts
For More Information On This Product,
Go to: www.freescale.com
Advance Information
45