MC68HC05P18 Datasheet, PDF (51/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Resets
Internal Resets
of this 4064 PH2 clock cycle delay, the RST signal will remain active until
the other reset condition(s) end.
5.4.2 Computer Operating Properly (COP) Reset
When the COP watchdog timer is enabled (by MOR1, bit 0), the internal
COP reset is generated automatically by a timeout of the COP watchdog
timer. This timer is implemented with an 18-stage ripple counter that
provides a timeout period of 65.5 ms when a 4-MHz oscillator is used.
The COP watchdog counter is cleared by writing a logical 0 to bit zero at
location $3FF0.
The COP register is shared with the most significant bit (MSB) of an
unimplemented user interrupt vector as shown in Figure 5-2. Reading
this location will return the MSB of the unimplemented user interrupt
vector. Writing to this location will clear the COP watchdog timer.
Address: $3FF0
Bit 7
6
5
4
3
2
1
Read: 0
0
0
0
0
0
0
Write: R
Reset: —
—
—
—
—
—
—
= Unimplemented
R = Reserved
Figure 5-2. Unimplemented Vector and COP
Watchdog Timer Register
Bit 0
0
COPR
—
5.4.3 Low-Voltage Reset (LVR)
If the LVR has been enabled via MOR1, the internal LVR reset is
generated when the supply voltage to the V_DD pin falls below a nominal
3.80 Vdc. The LVR threshold is not intended to be an accurate and
stable trip point, but is intended to ensure that the CPU will be held in
reset when the V_DD supply voltage is below reasonable operating limits.
If the LVR is tripped for a short time, the LVR reset signal will last at least
two cycles of the CPU bus clock, PH2.
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
Resets
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Advance Information
51