MC68HC05P18 Datasheet, PDF (101/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Input/Output Port (SIOP)
SIOP Signal Format
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
SDO
SCK
100 ns
100 ns
SDI
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Figure 11-2. SIOP Timing Diagram
The master and slave modes of operation differ only by the sourcing of
SCK. In master mode, SCK is driven from an internal source within the
MCU. In slave mode, SCK is driven from a source external to the MCU.
The SCK frequency is programmable via the mask option register 1
(MOR1). Available rates are OSC divided by 2, 4, 8, or 16.
NOTE: OSC divided by 2 is four times faster than the standard rate available on
the 68HC05P6.
Refer to 8.5 Mask Option Registers for a description of available mask
option registers.
11.3.2 Serial Data Input (SDI)
The SDI pin becomes an input as soon as the SIOP subsystem is
enabled. New data is presented to the SDI pin on the falling edge of
SCK. Valid data must be present at least 100 nanoseconds before the
rising edge of SCK and remain valid for 100 nanoseconds after the rising
edge of SCK. See Figure 11-2.
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
Serial Input/Output Port (SIOP)
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Advance Information
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