MC68HC05P18 Datasheet, PDF (33/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Memory
Input/Output and Control Registers
Addr.
Register Name
Bit 7
6
$0017
Output Compare LSB ^{Read: OCRL7}
Register (OCRL) Write:
See page 90. _Reset:
OCRL6
$0018
Timer MSB Register ^{Read: TMRH7}
(TMRH) Write:
See page 88. _{Reset: 1}
TMRH6
1
$0019
Timer LSB Register ^{Read: TMRL7}
(TMRL) Write:
See page 88. _{Reset: 1}
TMRL6
1
$001A
Alternate Counter MSB ^{Read: ACRH7}
Register (ACRH) Write:
See page 88. _{Reset: 1}
ACRH6
1
$001B
Alternate Counter LSB ^{Read: ACRL7}
Register (ACRL) Write:
See page 88. _{Reset: 1}
ACRL6
1
$001C
EEPROM Programming ^{Read: 0}
Register (EEPROG) Write:
See page 72. _{Reset: 0}
CPEN
0
A/D Conversion Data Register ^{Read: AD7 AD6}
$001D
(ADC) Write:
See page 84. _Reset:
$001E
A/D Status and Control ^{Read: CC}
R
Register (ADSC) Write:
See page 82. _{Reset: 0}
0
$001F
Reserved
R
R
5
OCRL5
TMRH5
1
TMRL5
1
ACRH5
1
ACRL5
1
0
0
AD5
ADON
0
R
4
OCRL4
3
OCRL3
Unaffected by reset
TMRH4 TMRH3
1
TMRL4
1
TMRL3
1
ACRH4
1
ACRH3
1
ACRL4
1
ACRL3
1
1
ER1
ER0
0
0
AD4
AD3
Unaffected by reset
0
0
0
0
R
R
2
1
Bit 0
OCRL2 OCRL1 OCRL0
TMRH2 TMRH1 TMRH0
1
1
1
TMRL2 TMRL1 TMRL0
1
0
0
ACRH2 ACRH1 ACRH0
1
1
1
ACRL2 ACRL1 ACRL0
1
0
0
LATCH EERC EEPGM
0
0
0
AD2 AD1 AD0
CH2 CH1 CH0
0
0
0
R
R
R
= Unimplemented
R = Reserved
Figure 2-4. I/O and Control Registers (Sheet 3 of 3)
U = Unaffected
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
Memory
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Advance Information
33