MC68HC05P18 Datasheet, PDF (95/144 Pages) Freescale Semiconductor, Inc – Advance Information

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16-Bit Timer
Timer Status Register
ICIE — Input Capture Interrupt Enable Bit
Bit 7, when set, enables input capture interrupts to the CPU. The
interrupt will occur at the same time bit 7 (ICF) in the TSR register is
set.
OCIE —Output Compare Interrupt Enable Bit
Bit 6, when set, enables output compare interrupts to the CPU. The
interrupt will occur at the same time bit 6 (OCF) in the TSR register is
set.
TOIE — Timer Overflow Interrupt Enable Bit
Bit 5, when set, enables timer overflow (rollover) interrupts to the
CPU. The interrupt will occur at the same time bit 5 (TOF) in the TSR
register is set.
IEDG — Input Capture Edge Select Bit
Bit 1 selects which edge of the input capture signal will trigger a
transfer of the contents of the free-running counter registers to the
input capture registers. Clearing this bit will select the falling edge;
setting it selects the rising edge.
OLVL — Output Compare Output Level Select Bit
Bit 0 selects the output level (high or low) that is clocked into the
output compare output latch at the next successful output compare.
10.7 Timer Status Register
Reading the timer status register (TSR) satisfies the first condition
required to clear status flags and interrupts. See Figure 10-11. The only
remaining step is to read (or write) the register associated with the active
status flag (and/or interrupt). This method does not present any
problems for input capture or output compare functions.
However, a problem can occur when using a timer interrupt function and
reading the free-running counter at random times to, for example,
measure an elapsed time. If the proper precautions are not designed into
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
16-Bit Timer
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Advance Information
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