MC68HC05P18 Datasheet, PDF (61/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Operating Modes
COP Watchdog Timer Considerations
If the 16-bit timer interrupt is enabled, it will cause the processor to exit
wait mode and resume normal operation. The 16-bit timer may be used
to generate a periodic exit from wait mode. Wait mode may also be
exited when an IRQ or RESET occurs. Note that if port A interrupts (if
programmed as an option in the mask option register 1) will also exit wait
mode. However, when exiting wait mode, the internal oscillator will not
need to wait for 4064 PH2 clock cycles to stabilize as in the stop and halt
modes.
6.6 COP Watchdog Timer Considerations
The COP watchdog timer is active in user mode of operation when
programmed as an option in MOR1. Executing the STOP instruction
without conversion to halt (via mask option register1) will cause the COP
to be disabled. Therefore, it is recommended that the STOP instruction
be modified to produce halt mode (via MOR1) if the COP watchdog timer
will be enabled.
Furthermore, it is recommended that the COP watchdog timer be
disabled for applications that will use the halt or wait modes for time
periods that will exceed the COP timeout period.
COP watchdog timer interactions are summarized in Table 6-3.
Table 6-3. COP Watchdog Timer Recommendations
IF these conditions exist:
STOP Instruction Mode
Wait Period
THEN the COP
Watchdog Timer Should Be:
Halt mode selected
via MOR1, bit 5
WAIT period less than
COP timeout
Enable or disable COP
via MOR1, bit 0
Halt mode selected
via MOR1, bit 5
WAIT period more than
COP timeout
Disable COP
via MOR1, bit 0
Stop mode selected
via MOR1, bit 5
Any length wait period
Disable COP
via MOR1, bit 0
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
Operating Modes
For More Information On This Product,
Go to: www.freescale.com
Advance Information
61