MC68HC05P18 Datasheet, PDF (47/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Interrupts
Interrupt Types
If enabled, the PA0–PA7 pins will cause an IRQ interrupt only if these
individual pins are configured as inputs.
4.3.3.3 Input Capture Interrupt
The input capture interrupt is generated by the 16-bit timer as described
in Section 10. 16-Bit Timer. The input capture interrupt flag is located
in register TSR and its corresponding enable bit can be found in register
TCR. The I bit in the CCR must be clear in order for the input capture
interrupt to be enabled. The interrupt service routine address is specified
by the contents of memory locations $3FF8 and $3FF9.
4.3.3.4 Output Compare Interrupt
The output compare interrupt is generated by the 16-bit timer as
described in Section 10. 16-Bit Timer. The output compare interrupt
flag is located in register TSR and its corresponding enable bit can be
found in register TCR. The I bit in the CCR must be clear in order for the
output compare interrupt to be enabled. The interrupt service routine
address is specified by the contents of memory locations $3FF8 and
$3FF9.
4.3.3.5 Timer Overflow Interrupt
The timer overflow interrupt is generated by the 16-bit timer as described
in Section 10. 16-Bit Timer. The timer overflow interrupt flag is located
in register TSR and its corresponding enable bit can be found in register
TCR. The I bit in the CCR must be clear in order for the timer overflow
interrupt to be enabled. This internal interrupt will vector to the interrupt
service routine located at the address specified by the contents of
memory locations $3FF8 and $3FF9.
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
Interrupts
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Advance Information
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