MC68HC05P18 Datasheet, PDF (94/144 Pages) Freescale Semiconductor, Inc – Advance Information

16-Bit Timer
Freescale Semiconductor, Inc.
PH2
CLOCK
16-BIT
FREE-RUNNING
COUNTER
$FFEB
TCAP
PIN
$FFEC
$FFED
$FFEE
$FFEF
INPUT
CAPTURE
LATCH
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
FLAG
(SEE NOTE)
$????
$FFED
Note: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the input capture
flag is set during the next T11 timer state.
Figure 10-9. State Timing Diagram for Input Capture
10.6 Timer Control Register
The timer control (TCR) shown in Figure 10-10 and free-running counter
(TMRH, TMRL, ACRH, and ACRL) registers are the only registers of the
16-bit timer affected by reset. The output compare port (TCMP) is forced
low after reset and remains low until OLVL is set and a valid output
compare occurs.
Advance Information
94
Address: $0012
Bit 7
6
5
4
3
2
1
Read:
0
0
0
ICIE OCIE TOIE
IEDG
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 10-10. Timer Control Register (TCR)
Bit 0
OLVL
0
MC68HC(8)05P18 — Rev. 2.0
16-Bit Timer
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