MC68HC05P18 Datasheet, PDF (20/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
General Description
1.4 Mask Options
There are eight mask options on the MC68HC05P18 that are EEPROM
mask option register (MOR) selectable options for the MC68HC805P18.
For additional information, refer to 8.5 Mask Option Registers.
1. IRQ is edge- and level-sensitive or edge-sensitive only.
2. SIOP most-significant bit (MSB) first or least-significant bit (LSB)
first
3. SIOP clock rate set to oscillator divided by 2, 4, 8, or 16
4. COP watchdog timer enabled or disabled
5. STOP instruction enabled or converted to halt mode
6. Option to enable clock output pin to replace PD5
7. Option to individually enable pullups/interrupts on each of the
eight port A pins
8. Low-voltage reset (LVR) enabled or disabled
NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.
Any reference to voltage, current, or frequency specified in the following
sections will refer to the nominal values. The exact values and their
tolerance or limits are specified in Section 13. Electrical
Specifications.
1.5 Functional Pin Description
The following subsections describe the functionality of each pin on the
MC68HC05P18/MC68HC805P18 package. Pins connected to
subsystems described in other sections provide a reference to the
section instead of a detailed functional description.
The pinout is shown in Figure 1-2.
Advance Information
20
MC68HC(8)05P18 — Rev. 2.0
General Description
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