MC68HC05P18 Datasheet, PDF (76/144 Pages) Freescale Semiconductor, Inc – Advance Information

EEPROM
Freescale Semiconductor, Inc.
COPEN — COP Enable/Disable Bit
COPEN may be read at any time. In user mode, writing has no effect.
It has to be programmed in bootloader mode.
0 = The COP is disabled (erased state).
1 = The COP is enabled.
LEVIRQ — Interrupt Request Option Bit
LEVIRQ may be read at any time. In user mode, writing has no effect.
It has to be programmed in bootloader mode.
0 = The IRQ pin is edge-sensitive (erased state).
1 = The IRQ pin is edge- and level-sensitive.
LSBF — SIOP MSB or LSB First Bit
LSBF may be read at any time. In user mode, writing has no effect. It
has to be programmed in bootloader mode.
0 = The SIOP sends/receives MSB (bit 7) first (erased state).
1 = The SIOP sends/receives LSB (bit 0) first.
SPR1 and SPR0 — SIOP Rate Select Bits
These bits may be read at any time. In user mode, writing has no
effect. It has to be programmed in bootloader mode.
Table 8-2. SIOP Clock Rate Selection
SPR1
0
0
1
1
SPR0
0
1
0
1
Frequency
f_OSC divided by 16
f_OSC divided by 8
f_OSC divided by 4
f_OSC divided by 2
SWAIT — STOP Conversion to WAIT Bit
SWAIT may be read at any time. In user mode, writing has no effect.
It has to be programmed in bootloader mode.
0 = STOP instruction puts MCU in stop mode.
1 = STOP instruction puts MCU in halt mode.
Advance Information
76
MC68HC(8)05P18 — Rev. 2.0
EEPROM
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