MC68HC05P18 Datasheet, PDF (100/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Input/Output Port (SIOP)
HCO5 INTERNAL BUS
SPE
76543210
CONTROL
REGISTER
$0A
BAUD
RATE
GENERATOR
76543210
STATUS
REGISTER
$0B
76543210
8-BIT
SDO
SHIFT
REGISTER
SDI
$0C
I/O
CONTROL
LOGIC
SCK
PH2 CLOCK
Figure 11-1. SIOP Block Diagram
SDO/PB5
SDI/PB6
SCK/PB7
11.3 SIOP Signal Format
The SIOP subsystem is software configurable for master or slave
operation. No external mode selection inputs are available (such as the
slave select pin).
11.3.1 Serial Clock (SCK)
The state of the serial clock (SCK) output normally remains a logic 1
during idle periods between data transfers. The first falling edge of SCK
signals the beginning of a data transfer. At this time, the first bit of
received data is accepted at the SDI pin and the first bit of transmitted
data is presented at the SDO pin (see Figure 11-2). Data is captured at
the SDI pin on the rising edge of SCK, and the first bit of transmitted data
is presented at the SDO pin. The transfer is terminated upon the eighth
rising edge of SCK.
Advance Information
100
MC68HC(8)05P18 — Rev. 2.0
Serial Input/Output Port (SIOP)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA