MC68HC05P18 Datasheet, PDF (50/144 Pages) Freescale Semiconductor, Inc – Advance Information

Resets
Freescale Semiconductor, Inc.
IRQ
RESET
OSC
DATA
ADDRESS
V_DD
V_DD
(PULSE WIDTH = 4 x E-CLK)
D
LATCH
R
CLOCKED
PH2
ONE-SHOT
COP WATCHDOG
(COPR)
LOW-VOLTAGE
RESET (LVR)
POWER-ON RESET
(POR)
S
D
LATCH
PH2
Figure 5-1. Reset Block Diagram
TO IRQ
LOGIC
MODE
SELECT
CPU
TO OTHER
RST
PERIPHERALS
5.4 Internal Resets
The three internally generated resets are:
• Initial power-on reset (POR)
• Computer operating properly (COP) watchdog timer
• Low-voltage reset (LVR) functions
5.4.1 Power-On Reset (POR)
The internal POR is generated at power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
PH2 clock cycle oscillator stabilization delay after the oscillator becomes
active.
The POR will generate the RST signal and reset the MCU. The POR will
also pull the RESET pin low at the same time, allowing external devices
to be reset with the MCU. If any other reset function is active at the end
Advance Information
50
MC68HC(8)05P18 — Rev. 2.0
Resets
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