MC68HC05P18 Datasheet, PDF (113/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Instruction Set
Instruction Types
use a combination of direct addressing and relative addressing. The
direct address of the byte to be tested is in the byte following the opcode.
The third byte is the signed offset byte. The CPU finds the conditional
branch destination by adding the third byte to the program counter if the
specified bit tests true. The bit to be tested and its condition (set or clear)
is part of the opcode. The span of branching is from –128 to +127 from
the address of the next location after the branch instruction. The CPU
also transfers the tested bit to the carry/borrow bit of the condition code
register. Table 12-3 lists the jump and branch instructions.
Table 12-3. Jump and Branch Instructions
Instruction
Branch if carry bit clear
Branch if carry bit set
Branch if equal
Branch if half-carry bit clear
Branch if half-carry bit set
Branch if higher
Branch if higher or same
Branch if IRQ pin high
Branch if IRQ pin low
Branch if lower
Branch if lower or same
Branch if interrupt mask clear
Branch if minus
Branch if interrupt mask set
Branch if not equal
Branch if plus
Branch always
Branch if bit clear
Branch never
Branch if bit set
Branch to subroutine
Unconditional jump
Jump to subroutine
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
BIL
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRCLR
BRN
BRSET
BSR
JMP
JSR
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
Instruction Set
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Advance Information
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