MC68HC05P18 Datasheet, PDF (89/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
16-Bit Timer
Timer
The timer registers and alternate counter registers can be read at any
time without affecting their value. However, the alternate counter
registers differ from the timer registers in one respect: A read of the timer
register most significant bit (MSB) can clear the timer overflow flag
(TOF). Therefore, the alternate counter registers can be read at any time
without the possibility of missing timer overflow interrupts due to clearing
of the TOF. See Figure 10-4.
The free-running counter is initialized to $FFFC during reset and is a
read-only register. During power-on-reset (POR), the counter is
initialized to $FFFC and begins counting after the oscillator startup
delay. Because the counter is 16 bits preceded by a fixed divide-by-four
prescaler, the value in the counter repeats every 262,144 PH2 clock
cycles (524,288 oscillator cycles). When the free-running counter rolls
over from $FFFF to $0000, the timer overflow flag bit (TOF) in register
TSR is set. An interrupt can also be enabled when counter rollover
occurs by setting the timer overflow interrupt enable bit (TOIE) in register
TCR. See Figure 10-5.
PH2
CLOCK
16-BIT
FREE-RUNNING
COUNTER
$FFFE
$FFFF
$0000
$0001
$0002
TIMER
OVERFLOW
FLAG (TOF)
Note: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer status
register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register pair (TCRL).
Figure 10-4. State Timing Diagram for Timer Overflow
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
16-Bit Timer
For More Information On This Product,
Go to: www.freescale.com
Advance Information
89