MC68HC05P18 Datasheet, PDF (104/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Serial Input/Output Port (SIOP)
11.4.2 SIOP Status Register
This register is located at address $000B and contains two bits.
Figure 11-4 shows the position of each bit in the register and indicates
the value of each bit after reset.
Address: $000B
BIt 7
6
5
4
3
2
1
Bit 0
Read: SPIF DCOL
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-4. SIOP Status Register (SSR)
SPIF — Serial Port Interface Flag
SPIF is a read-only status bit that is set on the last rising edge of SCK
and indicates that a data transfer has been completed. It has no effect
on any future data transfers and can be ignored. The SPIF bit is
cleared by reading the SSR followed by a read or write of the SDR. If
the SPIF is cleared before the last rising edge of SCK, it will be set
again on the last rising edge of SCK. Reset clears the SPIF bit.
DCOL — Data Collision Bit
DCOL is a read-only status bit which indicates that an illegal access
of the SDR has occurred. The DCOL bit will be set when reading or
writing the SDR after the first falling edge of SCK and before SPIF is
set. Reading or writing the SDR during this time will result in invalid
data being transmitted or received.
The DCOL bit is cleared by reading the SSR (when the SPIF bit is set)
followed by a read or write of the SDR. If the last part of the clearing
sequence is done after another transfer has started, the DCOL bit will
be set again. Reset clears the DCOL bit.
Advance Information
104
MC68HC(8)05P18 — Rev. 2.0
Serial Input/Output Port (SIOP)
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