MC68HC05P18 Datasheet, PDF (92/144 Pages) Freescale Semiconductor, Inc – Advance Information

16-Bit Timer
Freescale Semiconductor, Inc.
This procedure prevents the output compare flag bit (OCF) from being
set between the time it is read and the time the output compare registers
are updated. A software example is shown in Figure 10-7.
9B
SEI
.
.
.
.
.
.
B6 XX LDA
BE XX LDX
B7 16 STA
B6 13 LDA
BF 17 STX
.
.
.
.
.
DATAH
DATAL
OCRH
TSR
OCRL
.
BLOCK INTERRUPTS
.
.
HI BYTE FOR COMPARE
LO BYTE FOR COMPARE
INHIBIT OUTPUT COMPARE
ARM OCF BIT TO CLEAR
READY FOR NEXT COMPARE
.
Figure 10-7. Output Compare Software Initialization Example
10.5 Input Capture
Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input
capture. They are used to latch the value of the free-running counter
after a defined transition is sensed by the input capture edge detector.
See Figure 10-8.
NOTE: The input capture edge detector contains a Schmitt trigger to improve
noise immunity.
The edge that triggers the counter transfer is defined by the input edge
bit (IEDG) in register TCR. Reset does not affect the contents of the
input capture registers. See Figure 10-10.
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the PH2 clock preceding
the external transition (see Figure 10-9). This delay is required for
internal synchronization. Resolution is affected by the prescaler,
allowing the free-running counter to increment once every four PH2
clock cycles.
Advance Information
92
MC68HC(8)05P18 — Rev. 2.0
16-Bit Timer
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA