MC68HC05L16 Datasheet, PDF (95/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10
LCD Driver
10.1 Introduction
The liquid crystal display (LCD) driver may be configured with four backplanes (BP) and 39 frontplanes
(FP) maximum. The V_DD voltage is the highest level of the output waveform and the lower three levels
are applied from VLCD1, VLCD2, and VLCD3 inputs.
On reset, LCD enable bit (LCDE) in the LCD control register (LCDCR) is cleared (LCD drivers at a
disabled state) and all BP pins and FP pins output V_DD levels.
The LCD clock is generated by the timebase module, and the LCLK bit in the TBCR1 selects the clock
frequency.
10.2 LCD Waveform Examples
Figure 10-1, Figure 10-2, Figure 10-3, and Figure 10-4 illustrate the LCD timing examples.
DUTY = 1/1 (STATIC)
BIAS = 1/1 (VLCD1 = V_DD, VLCD2 = VLCD3 = V_DD–VLCD)
1FRAME
BP0
V_DD, VLCD1
VLCD2, 3
FPx
(XXX1)
FPy
(XXX1)
V_DD, VLCD1
VLCD2, 3
V_DD, VLCD1
VLCD2, 3
BP0–FPx
(OFF)
+VLCD
0
–VLCD
BP0–FPy
(ON)
+VLCD
0
–VLCD
Figure 10-1. LCD 1/1 Duty and 1/1 Bias Timing Diagram
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
95