MC68HC05L16 Datasheet, PDF (82/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer System
9.2.6 Timer During Wait Mode
The CPU clock halts during wait mode, but timer 1 remains active. If interrupts are enabled, a timer
interrupt will cause the processor to exit wait mode.
9.2.7 Timer During Stop Mode
In stop mode, timer 1 stops counting and holds the last count value if STOP is exited by an interrupt. If
RESET is used, the counter is forced to $FFFC. During STOP, if at least one valid input capture edge
occurs at the TCAP pin, the input capture detect circuit is armed. This does not set any timer flags or wake
up the MCU. When the MCU does wake up, there is an active input capture flag and data from the first
valid edge that occurred during stop mode. If RESET is used to exit stop mode, then no input capture flag
or data remains, even if a valid input capture edge occurred.
9.3 Timer 2
Timer 2 is an 8-bit event counter which has one compare register, one event input pin (EVI), and one
event output pin (EVO). The event counter is clocked by the external clock (EXCLK) or prescaled system
clock (CLK2), selected by the T2CLK bit in the TCR2 register. The EXCLK may be EVI direct or EVI gated
by CLK2, which is selected by the IM2 bit at the EVI block (see 9.3.6 Timer Input 2 (EVI)).
Timer 2 may be used as a modulus clock divider with EVO pin, free-running counter (when compare
register is $00), or periodic interrupt timer.
The timer counter 2 (TCNT2) is an 8-bit up counter with preset input. The counter is preset to $01 by a
CMP2 signal from the comparator or by a CPU write to it that is done while the system clock (PH2) is low.
COUNTER
WRITE
CLK2 ⁰
S
E
1
EXCLK
L
$01
$01
COUNTER 2
T2CLK
TRANSFER
COMPARATOR 2
BUFFER 2
TRANSFER
CMP2
REGISTER (OC2)
Figure 9-5. Timer 2 Block Diagram
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
82
Freescale Semiconductor