MC68HC05L16 Datasheet, PDF (60/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Oscillators/Clock Distributions
7.3 System Clock Control
The system clock is provided for all internal modules except timebase. Both OSC and XOSC are available
as the system clock source. The divide ratio is selected by the SYS1 and SYS0 bits in the MISC register.
(See Table 7-1.)
By default, OSC/64 is selected on reset.
Table 7-1. System Bus Clock Frequency Selection
SYS1 SYS0
0
0
0
1
1
0
1
1
Divide Ratio
OSC ÷ 2
OSC ÷ 4
OSC ÷ 64
XOSC ÷ 2
CPU Bus Frequency (Hz)
OSC = 4.0 M OSC = 4.1943 M XOSC = 32.768 k
2.0 M
2.0972 M
—
1.0 M
1.0486 M
—
62.5 k
65.536 k
—
—
—
16.384 k
NOTE
Do not switch the system clock to XOSC (SYS1 and SYS0 = 11) when
XOSC clock is not available. The XOSC clock is available when STUP flag
is set.
Do not switch the system clock to OSC (SYS1 and SYS0 = 00, 01, or 10)
when OSC clock is not available. The OSC clock is available when FTUP
flag is set.
7.4 OSC and XOSC
The secondary oscillator (XOSC) runs continuously after power up. The main oscillator (OSC) can be
stopped to conserve power via the STOP instruction or the FOSCE bit in the MISC register. The effects
of restarting the OSC will vary depending on the current state of the MCU, including SYS0, SYS1, and
FOSCE.
7.4.1 OSC on Line
If the system clock is OSC, FOSCE should remain logic 1. Executing the STOP instruction in this condition
will halt OSC, put the MCU into a low-power mode, and clear the 6-bit POR counter. The 7-bit divider is
not initialized. Exiting STOP with external IRQ or reset re-starts the oscillator. When the POR counter
overflows, internal reset is released and execution can begin. The stabilization time will vary between
8064 and 8192 counts.
NOTE
Exiting STOP with external reset will always return the MCU to the state as
defined by the default register definitions, for example,
SYS0:SYS1 = 1:0, FOSCE = 1.
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
60
Freescale Semiconductor