MC68HC05L16 Datasheet, PDF (88/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer System
9.3.4 Timer Counter Register 2
Address: $001F
BIt 7
6
5
4
3
2
1
Bit 0
Read:
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Write:
Reset: 0
0
0
0
0
0
0
1
Figure 9-11. Timer Counter Register 2 (TCNT2)
TCNT2 is incremented by the falling edge of the timer clock, which is synchronized and has the same
timing as the falling edge of PH2.
The TCNT2 register is compared with the OC2 buffer register and initialized to $01 if it matches. It is also
initialized to $01 on reset and any CPU write to this register.
The CPU read of this counter should be done while PH2 is high. Data may be latched by the local or main
data bus while PH2 is low.
9.3.5 Timebase Control Register 1
Address: $0010
BIt 7
6
5
4
3
2
1
Bit 0
Read:
TBCLK
0
LCLK
0
0
0
T2R1
T2R0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 9-12. Timebase Control Register 1 (TBCR1)
T2R1/T2R0 — Prescale Rate Select Bits for Timer 2
The T2R1 and T2R0 bits select prescale rate of CLK2 for timer 2 and timer input 2. These bits are
cleared on reset.
Table 9-2. Timebase Prescale Rate Selection
T2R1
0
0
1
1
T2R0
0
1
0
1
System Clock
Divided by
1
4
32
256
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
88
Freescale Semiconductor