MC68HC05L16 Datasheet, PDF (70/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Simple Serial Peripheral Interface (SSPI)
After 8-bit data is shifted in/out, SCK stops and SPIF is set. If SPIE is enabled, an interrupt request is
generated. The slave device in stop mode wakes up by this interrupt. Further transfers (writes to SPDR)
are inhibited while SPIF is a logic 1.
The master-slave basic interconnection is illustrated in Figure 8-1.
MASTER DEVICE
SPDR
HFF
SDO
SDI
SLAVE DEVICE
SPDR
HFF
CLOCK
GENERATOR
SCK SCK
SDI
SDO
CLOCK
GENERATOR
Figure 8-1. SSPI Master-Slave Interconnection
8.4 Internal Block Descriptions
This following paragraphs describe the main blocks in the SSPI module. (See Figure 8-2).
INTERRUPT
CONTROLS AND
ADDRESS BUS
CONTROL LOGIC
HC05 INTERNAL BUS
DATA BUS
0 000 00
00 0
SPSR
SPCR
SPDR
HFF
SDO
SD
SS
MS
PC
TP
SP
IO
AE
TR
FL
R
T
R
DORD
SDI
CLOCK GENERATOR
SCK
Figure 8-2. SSPI Block Diagram
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
70
Freescale Semiconductor