MC68HC05L16 Datasheet, PDF (56/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output (I/O)
6.5.1 Port D Data Register
Address: $0003
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PD7
PD6
PD5
PD4
PD3
PD2
PD1
1
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 6-7. Port D Data Register (PORTD)
Read
Anytime; returns output data latch; bit 0 is always read logic 1
Write
Anytime (Writes do not change pin state when configured for LCD driver output.)
Reset
All bits set to logic 1 and output ports disconnected from the pins (LCD is enabled on reset.)
6.5.2 Port D MUX Register
Address: Option Map — $0003
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PDM7 PDM6 PDM5 PDM4
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 6-8. Port D MUX Register (PDMUX)
Read
Anytime (When OPTM = 1, bits 3–0 always read logic 0.)
Write
Anytime (Writes have no effect if PDH is set.)
Reset
All bits cleared; LCD enabled
PDMx — Port D MUX Control bit x
0 = Configure pin PDx to LCD
1 = Configure pin PDx to output
6.6 Port E
Port E pins serve one of two basic functions depending on the MCU mode selected:
• LCD frontplane driver outputs
• General-purpose output pins
Since port E is an output-only port, there is no DDRE register. Instead of DDRE, port E MUX control
register (PEMUX) is used. Bits 7–0 of this register control the port/LCD muxing of port E bits 7–0
respectively on a bit-wide basis. These bits are cleared on reset, and writing a logic 1 to any bit will turn
that pin into a port output. This function is superseded by the PEH and PEL bits in the LCD control register.
When PEH is set, the upper four bits of port E become port outputs regardless of the state of the PEMUX
bits. Likewise, when PEL is set, the lower four bits of port E become outputs.
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
56
Freescale Semiconductor