MC68HC05L16 Datasheet, PDF (86/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer System
IM2 — Timer Input 2 Mode Select
The IM2 bit selects whether EVI input is gated or not gated by CLK2. This bit is cleared on reset.
0 = EVI not gated by CLK2 (event mode)
1 = EVI gated by CLK2 (gate mode)
IL2 — Timer Input 2 Active Edge (Level) Select
The IL2 bit selects the active edge of EVI to increment the counter for event mode (IM2 = 0) or gate
enable level of EVI for gate mode
(IM2 = 1). This bit is cleared on reset.
0 = Falling edge selected (event mode)
Low level enables counting (gate mode)
1 = Rising edge selected (event mode)
High level enables counting (gate mode)
Table 9-1. EVI Modes Selection
IM2 IL2
Action on Clock
0
0 Falling edge of EVI increments counter
0
1 Rising edge of EVI increments counter
1
0 Low level on EVI enables counting
1
1 High level on EVI enables counting
OE2 — Timer Output 2 (EVO) Output Enable
The OE2 bit enables EVO output on the PC5 pin. When this bit is changed, control of the pin is delayed
(synchronized) until the next active edge of EVO is selected by the OL2 bit. This bit is cleared on reset.
0 = EVO output disabled
1 = EVO output enabled
OL2 — Timer Output 2 Edge Select for Synchronization
The OL2 bit selects which edge of EVO clock should be synchronized by the OE2 bit control. The OL2
bit also decides the initial value of the CMP2 divider, when counter 2 is written to by the CPU. This bit
is cleared on reset.
0 = The falling edge of EVO switches EVO output and PC5 if the OE2 bit has been changed.
1 = The rising edge of EVO switches EVO output and PC5 if the OE2 bit has been changed.
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
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Freescale Semiconductor