MC68HC05L16 Datasheet, PDF (85/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer 2
The CLK2 from the prescaler or the EXTCLK from the EVI block is selected as timer clock by the T2CLK
bit in the TCR2 register. The CLK2 and the EXCLK are synchronized to the falling edge of system clock
in the prescaler and the EVI blocks. The minimum pulse width of CLK2 is the same as the system clock,
and the minimum pulse width of EXCLK (event mode) is one PH2 cycle. When the EXCLK (event mode)
is selected, 50% duty is not guaranteed.
The counter is incremented by the falling edge of the timer clock and the period between two falling edges
is defined as one timer cycle in the following description.
The compare register (OC2) is provided for comparison with the timer counter 2 (TCNT2). The OC2 data
is transferred to the buffer register when the counter is preset by a CPU write or by a compare output
(CMP2). This buffer register is compared with the timer counter 2 (TCNT2).
The comparison between the counter and the OC2 buffer register is done when the system clock is high
in each bus cycle. If the counter matches with the OC2 buffer register, the comparator latches this result
during the current timer cycle. When the next timer cycle begins, the comparator outputs CMP2 signal (if
the compare match is detected during previous timer cycle). This CMP2 is used in the counter preset data
transfer to the buffer register, setting OC2F in the TSR2 and the EVO block. The counter preset overrides
the counter increment.
The OC2F bit may generate interrupt requests if the OC2IE bit in the TCR2 is set.
9.3.1 Timer Control Register 2
Address: $001C
BIt 7
6
5
4
3
2
1
Bit 0
Read:
TI2IE
OC2IE
0
T2CLK
IM2
IL2
OE2
OL2
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 9-8. Timer Control Register 2 (TCR2)
TI2IE — Timer Input 2 Interrupt Enable
The TI2IE bit enables timer input 2 (EVI) interrupt when TI2F is set. This bit is cleared on reset.
0 = Timer input 2 interrupt disabled
1 = Timer input 2 interrupt enabled
OC2IE — Compare 2 Interrupt Enable
The OC2IE bit enables compare 2 (CMP2) interrupt when compare match is detected (OC2F is set).
This bit is cleared on reset.
0 = Timer input 2 interrupt disabled
1 = Timer input 2 interrupt enabled
Bit 5 — Reserved
This bit is not used and is always read as logic 0.
T2CLK — Timer 2 Clock Select
The T2CLK bit selects the clock source for the timer counter 2. This bit is cleared on reset.
0 = CLK2 from prescaler selected
1 = EXCLK from EVI input block selected
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
85