MC68HC05L16 Datasheet, PDF (65/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

7.5.5 Timebase Control Register 1
Timebase
Address: $0010
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TBCLK
0
LCLK
0
0
0
T2R1
T2R0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 7-5. Timebase Control Register 1 (TBCR1)
Read
Anytime
Write
Anytime (Only one write is allowed on bit 7 after reset.)
TBCLK — Timebase Clock
The TBCLK bit selects the timebase clock source. This bit is cleared on reset. After reset, write to this
bit is allowed only once.
0 = XOSC clock selected
1 = OSC clock divided by 128 selected
Bit 6 — Reserved
This bit is not used and always reads as logic 0.
LCLK — LCD Clock
The LCLK bit selects the clock for the LCD driver. This bit is cleared on reset.
0 = Divide by 64 selected
1 = Divide by 128 selected
Bits 4–2 — Reserved
These bits are not used and always read as logic 0.
T2R1 and T2R0 — Timer 2 Prescale Rate Select Bits
T2R1 and T2R0 select timer 2 clock rate. See 9.3 Timer 2 for more detail.
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
65