MC68HC05L16 Datasheet, PDF(63/146 Page) Freescale Semiconductor, Inc

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MC68HC05L16 Datasheet, PDF (63/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Timebase

7.5 Timebase

Timebase is a 14-bit up-counter which is clocked by XOSC input or OSC input divided by 128. TBCLK bit

in the TBCR1 register selects the clock source.

This 14-bit divider is initialized to $0078 only upon power-on reset (POR). After counting 8072 clocks, the

STUP bit in the MISC register is set.

The divided clocks from the timebase are used for LCDCLK, STUP, TBI, and COP. (See Figure 7-4).

7.5.1 LCDCLK

The clocks divided by 64 and 128 are used as LCD clocks at the LCD driver module, and clocks are

selected by the LCLK bit in the TBCR1.

TBCLK

LCLK

OSC/27

XCLK

SEL

1/26

7-BIT

DIVIDER

1/27

SEL

LCD

CLOCK

TBR1

TBIE

1/20

7-BIT

1/25

SEL

DIVIDER

1/26

1/27

TBIF

TBI

COP CLEAR

TBR0

DIVIDE BY 4

COP

RESET

COP ENABLE

Figure 7-4. Timebase Clock Divider

7.5.2 STUP

Timebase divider is initialized to $0078 by the power-on detection. When the count reaches 8072, the

STUP flag in the MISC register is set. Once the STUP flag is set, it is never cleared until power down.

7.5.3 TBI

Timebase interrupts may be generated every 0.5, 0.25, 0.125, or 0.0039 seconds with a 32.768-kHz

crystal at XOSC pins.

The timebase interrupt flag (TBIF) is set every period and interrupt is requested if the enable bit (TBIE) is

set. The clock divided by 128, 4096, 8192, or 16,384 is used to set TBIF, and this clock is selected by the

TBR1 and TBR0 bits in the TBCR2 register. (See Table 7-3.)

MC68HC05L16 â¢ MC68HC705L16 Data Sheet, Rev. 4.1

Freescale Semiconductor

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