MC68HC05L16 Datasheet, PDF (26/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Serial Peripheral Status Register ^{Read: SPIF}
DCOL
0
0
0
0
0
0
$000B
(SPSR) Write:
See page 74. _{Reset: 0}
0
0
0
0
0
0
0
Serial Peripheral Data Register (SP- ^Read: _MSB
BIT 6 BIT 5
BIT 4
BIT 3
BIT 2 BIT 2
LSB
$000C
DR) Write:
See page 75. _Reset:
Unaffected by reset
$000D
Reserved
R
R
R
R
R
R
R
R
↓
$000F
Reserved
R
R
R
R
R
R
R
R
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
Timebase Control Register 1 ^Read:
(TBCR1) Write:
See page 88. _Reset:
Timebase Control Register 2 ^Read:
(TBCR2) Write:
See page 88. _Reset:
Timer Control Register ^Read:
(TCR) Write:
See page 80. _Reset:
Timer Status Register ^Read:
(TSR) Write:
See page 81. _Reset:
Input Capture Register High ^Read:
(ICH) Write:
See page 80. _Reset:
Input Capture Register Low ^Read:
(ICL) Write:
See page 80. _Reset:
Output Compare Register 1 High ^Read:
(OC1H) Write:
See page 79. _Reset:
Output Compare Register 1 Low ^Read:
(OC1L) Write:
See page 79. _Reset:
Timer Counter Register High ^Read:
(TCNTH) Write:
See page 88. _Reset:
TBCLK
0
TBIF
0
ICIE
0
ICF
U
BIT 15
BIT 7
BIT 15
BIT 7
BIT 15
0
0
TBIE
0
OC1IE
0
OC1F
U
BIT 14
BIT 6
BIT 14
BIT 6
BIT 14
LCLK
0
TBR1
1
TOIE
0
TOF
0
0
TBR0
1
0
0
0
0
0
0
RTBIF
0
0
0
0
U
BIT 13
0
BIT 12
0
BIT 11
Unaffected by reset
BIT 5 BIT 4 BIT 3
BIT 13
BIT 5
BIT 13
Unaffected by reset
BIT 12 BIT 11
Unaffected by reset
BIT 4 BIT 3
Unaffected by reset
BIT 12 BIT 11
Unaffected by reset
0
0
0
0
0
0
0
0
BIT 10
BIT 2
BIT 10
BIT 2
BIT 10
T2R1
0
0
COPE
0
IEDG
U
0
0
BIT 9
BIT 1
BIT 9
BIT 1
BIT 9
T2R0
0
0
COPC
0
OLVL
0
0
0
BIT 8
BIT 0
BIT 8
BIT 0
BIT 8
= Unimplemented
R = Reserved
Figure 2-3. Main I/O Map (Sheet 2 of 5)
U = Unaffected
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
26
Freescale Semiconductor