MC68HC05L16 Datasheet, PDF (41/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Interrupts
Figure 4-2 shows an example of IRQ1 interrupt. In this case, the interrupt occurs after execution the
instruction following the instruction which sets IRQ1E bit. The similar action occurs against IRQ2 and KWI
interrupts.
.
.
CLI
BSET IRQ1E, INTCR
LDA #$55
.
.
.
IRQ1 interrupt pending
Interrupt occurs after this instruction
Figure 4-2. IRQ Timing Delay
This problem can be solved by using a software patch like Figure 4-3. A similar procedure could be used
for IRQ2 or KWI.
.
.
CLI
BSET IRQ1E, INTCR
NOP
LDA #$55
.
.
IRQ1 interrupt pending
Interrupt occurs after this instruction
Figure 4-3. Software Patch for IRQ1
4.2.4 Timer 1 Interrupt
Three timer 1 interrupts (TOI, ICI, and OC1I) share the same interrupt vector at $FFF6 and $FFF7. See
9.2 Timer 1.
4.2.5 Timer 2 Interrupt
Two timer 2 interrupts (TI2I and OC2I) share the same interrupt vector at $FFF4 and $FFF5. See 9.3.1
Timer Control Register 2.
4.2.6 SSPI Interrupt
The SSPI transfer complete interrupt uses the vector at $FFF2 and $FFF3. See Chapter 8 Simple Serial
Peripheral Interface (SSPI).
4.2.7 Timebase Interrupt
The timebase interrupt uses the vector at $FFF0 and $FFF1. See 7.5 Timebase.
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
41