MC68HC05L16 Datasheet, PDF (64/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Oscillators/Clock Distributions
Table 7-3. Timebase Interrupt Frequency
TBCR2
TBR TBR
1
0
0
0
0
1
1
0
1
1
Divide Ratio
TBCLK ÷ 128
TBCLK ÷ 4096
TBCLK ÷ 8192
TBCLK ÷ 16,384
OSC = 4.0 M
244
7.63
3.81
1.91
Frequency (Hz)
OSC = 4.1943 M XOSC = 32.768 k
256
256
8.00
8.00
4.00
4.00
2.00
2.00
7.5.4 COP
The computer operating properly (COP) watchdog timer is controlled by the COPE and COPC bits in the
TBCR2 register.
The COP uses the same clock as TBI that is selected by the TBR1 and TBR0 bits. The TBI is divided by
four and overflow of this divider generates COP timeout reset if the COP enable (COPE) bit is set. The
COP timeout reset has the same vector address as POR and external RESET. To prevent the COP
timeout, the COP divider is cleared by writing a logic1 to the COP clear (COPC) bit.
When the timebase divider is driven by the OSC clock, clock for the divider is suspended during stop
mode or when FOSCE is a logic 0. This may cause COP period stretching or no COP timeout reset when
processing errors occur. To avoid these problems, it is recommended that the XOSC clock be used for
the COP functions.
When the timebase (COP) divider is driven by the XOSC clock, the divider does not stop counting and
the COPC bit must be triggered to prevent the COP timeout.
TBCR2
TBR1 TBR0
0
0
0
1
1
0
1
1
Table 7-4. COP Timeout Period
OSC = 4.0 MHz
Min
Max
12.3
16.4
393
524
786
1048
1573
2097
COP Period (ms)
OSC = 4.1943 MHz
Min
Max
11.7
15.6
375
500
750
1000
1500
2000
XOSC = 32.768 kHz
Min
Max
11.7
15.6
375
500
750
1000
1500
2000
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
64
Freescale Semiconductor