MC68HC05L16 Datasheet, PDF (66/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Oscillators/Clock Distributions
7.5.6 Timebase Control Register 2
Address:
Read:
Write:
Reset:
$0011
Bit 7
6
5
4
3
2
1
TBIF
0
0
TBIE
TBR1
TBR0
0
RTBIF
COPE
0
0
1
1
0
0
0
= Unimplemented
Figure 7-6. Timebase Control Register 2 (TBCR2)
Bit 0
0
COPC
0
Read
Anytime (Bits 3 and 0 are write-only bits and always read as logic 0.)
Write
Anytime (Bit 7 is a read-only bit and write has no effect; bit 1 is 1-time write bit.)
TBIF — Timebase Interrupt Flag
The TBIF bit is set every timeout interval of the timebase counter. This read-only bit is cleared by
writing a logic 1 to the RTBIF bit. Reset clears the TBIF bit. The timebase interrupt period between
reset and the first TBIF depends on the time elapsed during reset, since the timebase divider is not
initialized on reset.
TBIE — Timebase Interrupt Enable
The TBIE bit enables the timebase interrupt capability. If TBIF = 1 and TBIE = 1, the timebase interrupt
is generated.
0 = Timebase interrupt disabled
1 = Timebase interrupt requested when TBIF = 1
TBR1 and TBR0 — Timebase Interrupt Rate Select
The TBR1 and TBR0 bits select one of four rates for the timebase interrupt period (see Table 7-3). The
TBS rate is also related to the COP timeout reset period. These bits are set to logic 1 on reset.
Table 7-5. Timebase Interrupt Frequency
TBCR2
TBR1 TBR0
0
0
0
1
1
0
1
1
Divide Ratio
TBCLK ÷ 128
TBCLK ÷ 4096
TBCLK ÷ 8192
TBCLK ÷ 16,384
OSC = 4.0 M
244
7.63
3.81
1.91
Frequency (Hz)
OSC = 4.1943 M XOSC = 32.768 k
256
256
8.00
8.00
4.00
4.00
2.00
2.00
RTBIF — Reset TBS Interrupt Flag
The RTBIF bit is a write-only bit and is always read as logic 0. Writing logic 1 to this bit clears the TBIF
bit and writing logic 0 to this bit has no effect.
Bit 2 — Reserved
This bit is not used and is always read as logic 0.
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
66
Freescale Semiconductor