MC68HC05L16 Datasheet, PDF (91/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer 2
9.3.7 Event Output (EVO)
The EVO pin is the clock output pin of timer 2. The compare output from the timer 2 (CMP2) is divided in
this block for 50% duty output signal. This 1/2 divider is initialized to the level of the OL2 bit when the timer
counter 2 is written to by the CPU (initialized). When the OE2 bit in the timer control register 2 (TCR2) is
set, the EVO output is activated, and, when OE2 is cleared, EVO is deactivated. These controls must be
done synchronously to the EVO output signal to avoid an incomplete pulse on the pin. The OL2 bit in the
TCR2 decides which edge of EVO should be synchronized.
When the DDRC5 bit is set or the synchronized output enable is high (clock on), the output buffer at the
EVO/PC5 pin is enabled. If the DDRC5 bit is set to 1, the pin state during the idling condition (clock off)
depends on the PC5 output data latch. If the DDRC5 bit is cleared, the pin becomes high impedance
during clock off.
OE2
OL2
DQ
C
DDRC5
CMP2
CNTR2
WRITE
1/2
1
SEL
0
PC5 (OUT)
Figure 9-15. EVO Block Diagram
PC5
EVO
PC5 (IN)
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
91