MC68HC05L16 Datasheet, PDF (75/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

8.6.3 Serial Peripheral Data Register
Port Function
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 2
LSB
Write:
Reset:
Unaffected by Reset
Figure 8-6. Serial Peripheral Data Register (SPDR)
Read
A read during transmission causes DCOL to be set.
Write
A write during transmission causes DCOL to be set.
The SPDR is used to transmit and receive data on the serial bus.
In master mode, a write to this register initiates transmission/reception of a data byte.
The SPIF status bit is set at the completion of data byte transmission. A write to the SPDR is inhibited
while this register is shifting (a write attempt sets DCOL) or when the SPIF bit is set without reading SPSR.
Data collision never affects the receiving and transmitting data in SPDR.
A write or read of the SPDR after accessing the SPSR with SPIF set will clear the SPIF and DCOL bits.
The ability to access the SPDR is inhibited when a transmission is taking place. It is important to read the
discussion defining the DCOL and SPIF bits to understand the limits on using the SPDR.
When SSPI is not used (SPE = 0), the SPDR can be used as a general-purpose data storage register.
8.7 Port Function
The SSPI shares I/O pins with PC0–PC2. When SPE is set, PC0 becomes SDI input, PC1 becomes SDO
output and PC2 becomes SCK. The direction of SCK depends on the MSTR bit. Setting DDRC bits 0–2
does not change the data direction of the pin to output, but instead changes the source of data when
PC0–PC2 is read. If DDRCx = 1, port C bit x data latch is read and if DDRCx = 0, PORTCx pin level is
read by the CPU.
When SPE is clear, SSPI is disconnected from the I/O pins and PC0–PC2 are used as general-purpose
I/O pins. See 6.4 Port C.
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
75