MC68HC05L16 Datasheet, PDF (59/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7
Oscillators/Clock Distributions
7.1 Introduction
There are two oscillator blocks: OSC and XOSC. Several combinations of the clock distributions are
allowed for the modules in the MC68HC05L16. Refer to Figure 7-1.
FOSCE/
PWRON
OSC1
OSC2
OSC
1/2⁰
OSC DIVIDER
1/2¹
7-BIT
1/2⁵
SEL
1/2
WAIT
CPU
XOSC1
XOSC2
STOP
XOSC
CLK
CTRL
SYS1 SYS0
SYSTEM
CLOCK
POR
1/2⁷
6-BIT
1/2⁷
XCLK
FTUP
EXCLK
SSPI
TIMER 1
TIMER 2
TIMEBASE
Figure 7-1. Clock Signal Distribution
7.2 OSC Clock Divider and POR Counter
The OSC clock is divided by a 7-bit counter which is used for the system clock, timebase, and power-on
reset (POR) counter. Clocks divided by 2, 4, and 64 are available for the system clock selections and a
clock divided by 128 is provided for the timebase and POR counter.
The POR counter is a 6-bit clock counter that is driven by the OSC divided by 128. The overflow of this
counter is used for setting FTUP bit, releasing the POR, and resuming operation from stop mode.
The 7-bit divider and POR counter are initialized to $0078 by two conditions:
• Power-on detection
• When FOSCE bit is cleared
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
59