MC68HC05L16 Datasheet, PDF (67/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timebase
COPE — COP Enable
When the COPE bit is logic 1, the COP reset function is enabled. This bit is cleared on reset (including
COP timeout reset) and write to this bit is allowed only once after reset.
COPC — COP Clear
Writing logic 1 to the COPC bit clears the 2-bit divider to prevent COP timeout. (The COP timeout
period depends on the TBI rate.) This bit is a write-only bit and returns to logic 0 when read.
7.5.7 Miscellaneous Register
Address:
Read:
Write:
Reset:
$003E
Bit 7
6
5
FTUP
STUP
0
4
3
2
1
Bit 0
0
SYS1
SYS0 FOSCE OPTM
*
*
0
0
1
0
1
0
= Unimplemented
* Unaffected by reset but initialized by power-on reset
Figure 7-7. Miscellaneous Register (MISC)
FTUP — OSC Time Up Flag
Power-on detection and clearing the FOSCE bit clears this read-only bit. This bit is set by the overflow
of the POR counter. Reset does not affect this bit.
0 = During POR or OSC shut down
1 = OSC clock available for the system clock
STUP — XOSC Time Up Flag
Power-on detection clears this read-only bit. This bit is set after the timebase has counted 8072 clocks.
Reset does not affect this bit.
0 = XOSC not stabilized or no signal on XOSC1 and XOSC2 pins
1 = XOSC clock available for the system clock
Bits 5 and 4 — Reserved
These bits are not used and always read as logic 0.
SYS1 and SYS0 — System Clock Select
These two bits select the system clock source. On reset, the SYS1 and SYS0 bits are initialized to 1
and 0, respectively.
NOTE
Do not switch the system clock to XOSC (SYS1 and SYS0 = 11) when the
XOSC clock is not available. The XOSC clock is available when the STUP
flag is set.
Do not switch the system clock to OSC (SYS1 and SYS 0 = 00, 01, or 10)
when the OSC clock is not available. The OSC clock is available when the
FTUP flag is set.
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
67