MC68HC05L16 Datasheet, PDF (52/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output (I/O)
6.2 Port A
Port A is an 8-bit, bidirectional, general-purpose port. The data direction of a port A pin is determined by
its corresponding DDRA bit.
When a port A pin is programmed as an output by the corresponding DDRA bit, data in the PORTA data
register becomes output data to the pin. This data is returned when the PORTA register is read.
Open drain or CMOS outputs are selected by AWOMH and AWOML bits in the WOM1 register. If the
AWOMH bit is set, the P-channel drivers of bits 7–4 output buffers are disabled (open drain). If the
AWOML bit is set, the P-channel drivers of bits 3–0 output buffers are disabled (open drain).
When a bit is programmed as input by the corresponding DDRA bit, the pin level is read by the CPU.
Port A has optional pullup resistors. When the RAH bit or RAL bit in the RCR1 is set, pullup resistors are
attached to the upper four bits or lower four bits of port A pins, respectively. When a pin outputs a low
level, the pullup resistor is disconnected regardless of the RAH or RAL bit state.
6.2.1 Port A Data Register
Address: $0000
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Write:
Reset:
Unaffected by reset
Figure 6-2. Port A Data Register (PORTA)
Read
Anytime; returns pin level if DDR set to input; returns output data latch if DDR set to output
Write
Anytime; data stored in an internal latch; drives pin only if DDR set for output
Reset
Becomes high-impedance input
6.2.2 Port A Data Direction Register
Address: Option Map — $0000
Bit 7
6
5
4
3
2
1
Read:
DDRA7
Write:
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
Reset: 0
0
0
0
0
0
0
Figure 6-3. Port A Data Direction Register (DDRA)
Read
Anytime when OPTM = 1
Write
Anytime when OPTM = 1
Reset
Cleared to $00; all general-purpose I/O configured for input
Bit 0
DDRA0
0
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
52
Freescale Semiconductor