MC68HC05L16 Datasheet, PDF (57/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port E
On reset, all port E outputs are disconnected from the pins and the port E data latches are set to logic 1.
If EWOMH bit or EWOML bit in the WOM1 register is set, the P-channel driver of output buffers at the
upper or lower four bits, respectively, are disabled (open-drain mode). These open-drain controls do not
apply to the pins which are configured as frontplane driver outputs.
6.6.1 Port E Data Register
Address: $0004
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 6-9. Port E Data Register (PORTE)
Read
Anytime; returns output data latch
Write
Anytime (Writes do not change pin state when configured for LCD driver output.)
Reset
All bits set to logic 1 and output ports disconnected from the pins (LCD is enabled on reset.)
6.6.2 Port E MUX Register
Address: Option Map — $0004
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PEM7
Write:
PEM6
PEM5
PEM4
PEM3
PEM2
PEM1
PEM0
Reset: 0
0
0
0
0
0
0
0
Figure 6-10. Port E MUX Register (PEMUX)
Read
Anytime when OPTM = 1
Write
Anytime (Writes have no effect if PEH/PEL is set.)
Reset
All bits cleared (LCD is enabled.)
PEMx — Port E MUX Control Bit x
0 = Configure pin PEx to LCD
1 = Configure pin PEx to output
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
57