MC68HC05L16 Datasheet, PDF (53/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

DDRAx — Port A Data Direction Register Bit x
0 = Configure I/O pin PAx to input
1 = Configure I/O pin PAx to output
Port B
6.3 Port B
Port B pins serve two basic functions: KWI input pins and general-purpose input pins.
Each KWI input is enabled or disabled by the corresponding KWIEx bit in the KWIEN register, and the
usage of the KWI input does not affect the general-purpose input function.
Port B pin states may be read any time regardless of the configurations. Since there is no output drive
logic associated with port B, there is no DDRB register and the write to the PORTB register has no
meaning.
Port B has optional pullup resistors. When the RBH or RBL bit in the RCR1 is set, pullup resistors are
attached to the upper four bits or lower four bits of port A pins, respectively.
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Write:
Reset:
Unaffected by reset
Figure 6-4. Port B Data Register (PORTB)
Read
Anytime; returns pin level
Write
Has no meaning or effect
Reset
Unaffected; always an input port
6.4 Port C
Port C pins share functions with several on-chip peripherals. A pin function is controlled by the enable bit
of each associated peripheral.
Bit 7 and bit 6 of port C are general-purpose I/O pins and IRQ input pins. The DDRC7 and DDRC6 bits
determine whether the pin states or the data latch states should be read by the CPU. Since IRQ1F or
IRQ2F can be set by either the pins or the data latches, when using IRQs, be sure to clear the flags by
software before enabling the IRQ1E or IRQ2E bits.
When configured for output port, PC6 and PC7 are open drain only. When V_DD output is required, a pullup
resistor must be enabled.
The PC5 pin is a general-purpose I/O pin and the direction of the pin is determined by the DDRC5 bit in
the data direction register C (DDRC). When the event output (EVO) is enabled, the PC5 is configured as
an event output pin and the DDRC5 bit has meaning only for the read of PC5 bit in the PORTC register;
if the DDRC5 is set, the PC5 data latch is read by the CPU. Otherwise, PC5 pin level (EVO state) is read.
When EVO is disabled, the DDRC5 bit decides the idling state of EVO (if DDRC5 = 1).
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Freescale Semiconductor
53