MC68HC05L16 Datasheet, PDF (72/146 Pages) Freescale Semiconductor, Inc – Microcontrollers

Simple Serial Peripheral Interface (SSPI)
SCK
SDO
DORD = 0
SDI
DORD = 0
MSB BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 LSB
MSB BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 LSB
SDO
DORD = 1
LSB BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 MSB
SDI
DORD = 1
LSB BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 MSB
DATA
SAMPLE
Figure 8-3. SSPI Clock-Data Timing Diagram
8.5.2 Serial Clock (SCK)
SCK is used for synchronization of both input and output data streams through its SDI and SDO pins.
The master and slave devices are capable of exchanging a data byte during a sequence of eight clock
pulses. Since the SCK is generated by the master, slave data transfer is accomplished by synchronization
to SCK.
The master generates the SCK through a circuit driven by the internal processor clock and uses the SCK
to latch incoming slave device data on the SDI pin and shift out data to the slave via the SDO pin. The
SPR bit in the SPCR of the master selects the transmission clock rate.
The slave device receives the SCK from the master device, and uses the SCK to latch incoming master
device data on the SDI pin and shifts out data to the master via the SDO pin. The SPR bit in the SPCR of
the slave has no meaning.
NOTE
PC2/SCK should be at V_DD level before SSPI is enabled. This can be done
with an internal or external pullup resistor or by setting DDRC2 = 1 and PC2
= 1 prior to enabling the SSPI. Otherwise, the circuit will not initialize
correctly.
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
72
Freescale Semiconductor