MC908GR32AVFAE Datasheet, PDF (67/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
Table 3-1. Mux Channel Select⁽¹⁾ (Continued)
ADCH4
1
1
1
1
1
1
1
1
1
↓
1
1
1
1
ADCH3
0
0
0
0
0
0
0
0
1
↓
1
1
1
1
ADCH2
0
0
0
0
1
1
1
1
0
↓
1
1
1
1
ADCH1
0
0
1
1
0
0
1
1
0
↓
0
0
1
1
ADCH0
0
1
0
1
0
1
0
1
0
↓
0
1
0
1
Input Select
PTG0/AD16
PTG1/AD17
PTG2/AD18
PTG3/AD19
PTG4/AD20
PTG5/AD21
PTG6/AD22
PTG7/AD23
Unused
V_REFH
V_REFL
ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown or re-
served.
3.8.2 ADC Data Register High and Data Register Low
3.8.2.1 Left Justified Mode
In left justified mode, the ADRH register holds the eight MSBs of the
10-bit result. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH
and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches
the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL
reads are completed.
Address: $003D
Bit 7
6
5
4
3
2
Read: AD9
AD8
AD7
AD6
AD5
AD4
Write:
Reset:
Unaffected by reset
Address: $003E
Read: AD1
AD0
0
0
0
0
Write:
Reset:
Unaffected by reset
= Unimplemented
ADRH
1
Bit 0
AD3
AD2
ADRL
0
0
Figure 3-5. ADC Data Register High (ADRH) and Low (ADRL)
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor
67