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MC908GR32AVFAE Datasheet, PDF (282/314 Pages) Freescale Semiconductor, Inc – Microcontrollers
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Electrical Specifications
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Pullup/pulldown resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0,
PTD7/T2CH1–PTD0/SS
RPU
20
45
65
kΩ
Capacitance
Ports (as input or output)
COut
CIn
—
—
—
—
12
8
pF
Monitor mode entry voltage
VTST
VDD + 2.5
—
VDD + 4.0
V
Low-voltage inhibit, trip falling voltage
VTRIPF
2.35
2.6
2.8
V
Low-voltage inhibit, trip rising voltage
VTRIPR
2.4
2.66
2.9
V
Low-voltage inhibit reset/recover hysteresis
(VTRIPF + VHYS = VTRIPR)
VHYS
—
100
—
mV
POR rearm voltage(12)
VPOR
0
—
100
mV
POR reset voltage(13)
VPORRST
0
700
800
mV
POR rise time ramp rate(14)
RPOR
0.02
—
—
V/ms
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TA (min) to TA (max), unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 16 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOSC = 16 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
IDD. Measured with CGM and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All ports
configured as inputs. Typical values at midpoint of voltage range, 25°C only.
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 4 MHz). All inputs 0.2 V from
rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. This parameter is characterized and not tested on each device.
8. All functional non-supply pins are internally clamped to VSS and VDD.
9. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
10. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock
is present, or if clock rate is very low (which would reduce overall power consumption).
11. Pullups and pulldowns are disabled.
12. Maximum is highest voltage that POR is guaranteed.
13. Maximum is highest voltage that POR is possible.
14. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
282
Freescale Semiconductor
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