MC908GR32AVFAE Datasheet, PDF (142/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
12.5.3 Port C Input Pullup Enable Register
The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each
of the seven port C pins. Each bit is individually configurable and requires that the data direction register,
DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRC is configured for output mode.
Address: $000E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
Reset: 0
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-12. Port C Input Pullup Enable Register (PTCPUE)
PTCPUE6–PTCPUE0 — Port C Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port C pin configured to have internal pullup
0 = Corresponding port C pin internal pullup disconnected
12.6 Port D
Port D is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (SPI)
module and four of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software
configurable pullup devices if configured as an input port. PTD0 is shared with the MCLK output.
12.6.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight port D pins.
Address:
Read:
Write:
Reset:
Alternate Function:
$0003
Bit 7
PTD7
T2CH1
6
PTD6
T2CH0
5
PTD5
T1CH1
4
3
PTD4
PTD3
Unaffected by reset
T1CH0 SPSCK
2
PTD2
MOSI
Figure 12-13. Port D Data Register (PTD)
1
PTD1
MISO
Bit 0
PTD0
SS
MCLK
PTD7–PTD0 — Port D Data Bits
These read/write bits are software-programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
T2CH1 and T2CH0 — Timer 2 Channel I/O Bits
The PTD5/T2CH1–PTD4/T2CH0 pins are the TIM2 input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTD7/T2CH1–PTD6/T2CH0 pins are timer channel
I/O pins or general-purpose I/O pins. See Chapter 17 Timer Interface Module (TIM1) and Chapter 18
Timer Interface Module (TIM2).
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
142
Freescale Semiconductor