MC908GR32AVFAE Datasheet, PDF (237/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output Registers
Address: $0025
Bit 7
Read: CH0F
Write: 0
Reset: 0
T1SC0
6
CH0IE
0
5
MS0B
0
4
MS0A
0
3
2
ELS0B ELS0A
0
0
1
Bit 0
TOV0 CH0MAX
0
0
Address: $0028 T1SC1
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH1F
0
CH1IE
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 17-8. TIM1 Channel Status and Control Registers (T1SC0:T1SC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM1 counter registers matches the value in the TIM1 channel x registers.
Clear CHxF by reading the TIM1 channel x status and control register with CHxF set and then writing
a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing
0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of
CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM1 CPU interrupt service requests on channel x. Reset clears the CHxIE
bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1
channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and reverts T1CH1 to general-purpose
I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. See Table 17-2.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor
237