MC908GR32AVFAE Datasheet, PDF (270/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Development Support
Table 19-1. Monitor Mode Signal Requirements and Options
Mode
Serial
IRQ
RST
Reset
Vector
Communication
Mode
Selection
Divider
PLL
PTA0 PTA1 PTB0 PTB1 PTB4
COP
Communication
Speed
External Bus
Baud
Clock Frequency Rate
V_DD
V_TST or
X
1
Normal
V_TST
Monitor
V_DD
V_TST or
X
1
V_TST
0
1
0
0 OFF Disabled 4.0 MHz 2.0 MHz 7200
0
1
0
1 OFF Disabled 8.0 MHz 2.0 MHz 7200
Forced
Monitor
V_DD
or
V_SS
V_DD
$FF
(blank)
1
0
X
X
X OFF Disabled 8.0 MHz 2.0 MHz 7200
V_DD V_{DD Not}
User or or $FF
X
V_SS V_TST
X
X
X
X
X Enabled X
X
X
MON08
Function
[Pin No.]
V_TST
[6]
RST
[4]
—
COM
[8]
SSEL MOD0 MOD1 DIV4
[10] [12] [14] [16]
—
—
OSC1
[13]
—
—
1. PTA0 must have a pullup resistor to V_DD in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 7200. Baud rate using external oscillator is bus
frequency / 278.
3. External clock is a 4.0 MHz or 8.0 MHz crystal on OSC1 and OSC2 or a canned oscillator on OSC1.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
NC
1
2
GND
NC
3
4
RST
NC
5
6
IRQ
NC
7
8
PTA0
NC
9
10 PTA1
NC
11
12 PTB0
OSC1
13
14 PTB1
V_DD
15
16 PTB4
Enter monitor mode with pin configuration shown in Table 19-1 by pulling RST low and then high. The
rising edge of RST latches monitor mode. Once monitor mode is latched, the levels on the port pins
except PTA0 can change.
Once out of reset, the MCU waits for the host to send eight security bytes (see 19.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
270
Freescale Semiconductor