MC908GR32AVFAE Datasheet, PDF (146/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
RxD — SCI Receive Data Input
The PTE1/RxD pin is the receive data input for the ESCI module.
When the enable SCI bit, ENSCI, is clear, the ESCI module is disabled, and the PTE1/RxD pin is
available for general-purpose I/O. See Chapter 13 Enhanced Serial Communications Interface (ESCI)
Module.
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the ESCI module. When the enable SCI bit, ENSCI,
is clear, the ESCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
Chapter 13 Enhanced Serial Communications Interface (ESCI) Module.
12.7.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a
1 to a DDRE bit enables the output buffer for the corresponding port E pin; a 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$000C
Bit 7
6
5
4
3
2
1
0
0
DDRE5 DDRE4 DDRE3 DDRE2 DDRE1
0
0
0
0
0
0
0
= Unimplemented
Figure 12-18. Data Direction Register E (DDRE)
Bit 0
DDRE0
0
DDRE5–DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE5–DDRE0, configuring all port
E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 12-19 shows the port E I/O logic.
When bit DDREx is a 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a 0,
reading address $0008 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-6 summarizes the operation of the port E pins.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
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Freescale Semiconductor