MC908GR32AVFAE Datasheet, PDF (215/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

SPI During Break Interrupts
15.9.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by
reset, any transfer in progress is aborted, and the SPI is reset.
15.10 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. BCFE in the SIM break flag control register (SBFCR) enables software to clear status bits
during the break state. See Chapter 14 System Integration Module (SIM).
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE at 0 (its default state), software
can read and write I/O registers during the break state without affecting status bits. Some status bits have
a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the
bit cannot change during the break state as long as BCFE is 0. After the break, doing the second step
clears the status bit.
Since the SPTE bit cannot be cleared during a break with BCFE cleared, a write to the transmit data
register in break mode does not initiate a transmission nor is this data transferred into the shift register.
Therefore, a write to the SPDR in break mode with BCFE cleared has no effect.
15.11 I/O Signals
The SPI module has four I/O pins:
• MISO — Master input/slave output
• MOSI — Master output/slave input
• SPSCK — Serial clock
• SS — Slave select
15.11.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin
of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI
simultaneously receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is
configured as a slave when its SPMSTR bit is 0 and its SS pin is low. To support a multiple-slave system,
a high on the SS pin puts the MISO pin in a high-impedance state.
When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction
register of the shared I/O port.
15.11.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin
of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI
simultaneously transmits data from its MOSI pin and receives data on its MISO pin.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor
215