MC908GR32AVFAE Datasheet, PDF (193/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Exception Control
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 14-11 demonstrates what happens when two interrupts are pending. If an interrupt
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
CLI
LDA #$FF
BACKGROUND
ROUTINE
INT1
PSHH
PULH
RTI
INT1 INTERRUPT SERVICE ROUTINE
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 14-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
14.5.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
14.5.1.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 14-3 summarizes the
interrupt sources, hardware flag bits, hardware interrupt mask bits, interrupt status register flags, interrupt
priority, and exception vectors. The interrupt status registers can be useful for debugging.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor
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